1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and a method for manufacturing the same.
2. Background Art
Nonvolatile memory typified by NAND flash memory is used widely for large-capacity data storage in mobile telephones, digital still cameras, USB memory, silicon audio, and the like. The market continues to grow due to the reduction of manufacturing costs per bit enabled by rapid downscaling. NAND flash memory in particular has a small cell surface area of 4F2, where F is the minimum processing dimension (the half pitch); and rapid downscaling due to the simple structure thereof is progressing. However, bit density increase of future NAND flash memory will face many issues such as limitations on the downscaling of lithography, reduced reliability due to the transistor scaling, increased fluctuation of the transistor characteristics accompanying the transistor size downscaling, limitations on operation speed due to negative effects of downscaling such as short channel effects or narrow channel effects, and so on.
Conversely, P-A 2007-266143 (Kokai) discusses technology relating to a nonvolatile semiconductor storage device in which insulating films and charge storage layers are provided around a semiconductor of a columnar configuration, and multiple recording layers are stacked. However, in the case of this structure, it is necessary to pattern the gate electrode that selects the charge storage layer into a striped configuration in a plane parallel to the substrate. Therefore, the cell surface area thereof is 6F2 as compared to the cell surface area of normal NAND flash memory of 4F2 (where F is the half pitch). Further, in the case of the structure of P-A 2007-266143 (Kokai), downscaling is constrained by manufacturing process constraints when forming a silicon plug after forming the gate electrode. Then, forming the silicon plug after the gate electrode formation constrains the materials used in the gate electrode; and it is difficult to reduce the resistance. Therefore, it is necessary to make the gate electrode thick or increase the space between adjacent cells to prevent the depletion of the electrode. Thereby, downscaling is constrained. Moreover, an operation mechanism is different than that of NAND flash memory. Therefore, conventional peripheral circuit configurations of NAND flash memory will be re-designed before diversion